The MCM67M618B is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, highperformance, secondary cache for the MC68040 and PowerPCTM microprocessors. It is organized as 65,536 words of 18 bits, fabricated using Motorola's highperformance silicongate BiCMOS technology. The device integrates input registers, a 2bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 A15), data inputs (DQ0 DQ17), and all control sigDQ9 nals, except output enable (G), are clock (K) controlled through posiDQ10 VCC