The MCM67J518 is a 589,824 bit synchronous static random access memory designed to provide a burstable, highperformance, secondary cache for the i486TM and PentiumTM microprocessors. It is organized as 32,768 words of 18 bits, fabricated with Motorola's highperformance silicongate BiCMOS technology. The device integrates input registers, a 2bit counter, high speed SRAM, and high drive registered output drivers onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 A14), data inputs (D0 D17), and all control signals except output enable (G) are clock (K) controlled through positiveedgetriggered noninverting registers.