The MCM67B618B is a 1,179,648bit synchronous fast static random access memory designed to provide a burstable, highperformance, secondary cache for the i486TM and Pentiumr microprocessors. The MCM67B618B (organized as 65,536 words by 18 bits) is fabricated using Motorola's highperformance silicongate BiCMOS technology. The device integrates input registers, a 2bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 A15), data inputs (D0 D17), and all control signals except output enable (G) are clock (K) controlled through positive edgetriggered noninverting registers. DQ9