The ZBT RAM is a 4Mbit synchronous fast static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during backtoback read/write and write/read cycles. The MCM63Z737 is organized as 128K words of 36 bits each and the MCM63Z819 is organized as 256K words of 18 bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, a 2bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQ), and all control signals except output enable (G) and linear burst order (LBO) are clock (CK) controlled through positive edgetriggered noninverting registers. Write cycles are internally selftimed and are initiated by the rising edge of the clock (CK) input. This feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, a flowthrough SRAM allows output data to simply flow freely from the memory array.