The MCM62Y308 is a synchronous, dual ported memory organized as 8,192 words of 8 bits each, fabricated using Motorola's doublemetal, doublepoly, 0.65 m CMOS process. It is intended for high speed video or other applications which process data on a linebyline basis. Through the use of a single clock and port control inputs, separate read and write data ports provide simultaneous access to a common memory array. Simultaneous read/write access to the same address location is also allowed, with old data being read followed by a write of the new data. This allows multiple devices to be cascaded with the output of one directly driving the input of another. In this configuration the data stream can be tapped at strategic interconnect points to perform various digital filtering functions. Since there are no external address inputs, separate internal read and write address counters are provided as a means of indexing the memory array. These counters are preloaded and then selectively incremented or decremented by asserting read enable (RE) and write enable (WE) inputs, allowing cycle to cycle control. The address counters can be reloaded back to their initial values through the use of the read reload (RR ) and write reload (WR) control inputs. These inputs initiate the transfer of address reload register values into the address counters which index the memory array. When an address counter reaches 0000 it will roll over on the next count. On the down count the roll over condition will cause the rollover flag (WRF or RRF) to assert high. On the up count these flags must be treated as don't cares. The rollover flag outputs are cleared when their associated rollover reset pin is asserted low. The TDI input is used to write the reload registers using special test access port instructions. The read and write address counters are 16 bits long, and only 13 of the 16 bits are required to index the 8K deep memory array. The remaining three bits are used for depth expansion. These three bits are compared to the lower three bits in the control register, and as long as they are equal that port (i.e., read or write) will remain active. If the bits do not compare, the port will become inactive (i.e., for read outputs, highz; for write inputs, disabled) however, the counter will continue to count on the rising edge of K as long as the port enable signal (RE or WE) is asserted. The TDI input is used to write the control register using special test access port instructions. The output enable Input can be programmed to be either synchronous or asynchronous through the control register. The MCM62Y308 is available in a 32 pin SOJ package. 8K x 8 Fast Access Static Memory Array Single 5 V Power Supply -- MCM62Y30817: 5% Synchronous, Simultaneous Read/Write Memory Access 50 MHz Maximum Clock Cycle Time, < 15 ns Read Access Single Clock Operation