The MC74AC/ACT823 consists of nine D-type edge-triggered flip-flops. This device has 3-state outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enabled pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flips. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The MC74AC/ACT823 has Clear (CLR) and Clock Enable (EN) pins. These devices are ideal for parity bus interfacing in high performance systems. When CLR is LOW, and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. 3-State Outputs for Bus Interfacing Broad Side Pin Configuration