The MC14522B BCD counter and the MC14526B binary counter are constructed with MOS Pchannel and Nchannel enhancement mode devices in a monolithic structure. These devices are presettable, cascadable, synchronous down counters with a decoded "0" state output for dividebyN applications. In single stage applications the "0" output is applied to the Preset Enable input. The Cascade Feedback input allows cascade dividebyN operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock. These complementary MOS counters can be used in frequency synthesizers, phaselocked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic EdgeClocked Design -- Incremented on Positive Transition of Clock or Negative Transition of Inhibit Asynchronous Preset Enable