The MCM64AF32 is designed to provide 256K of asynchronous L2 cache for the Pentium microprocessor in conjunction with Intel's Triton chip set. The module is configured as 32K x 64 bits in a 160 pin card edge connector. The module uses eight Motorola 3.3 V 32K x 8 FSRAMs for the cache memory, one Motorola 5 V 32K x 8 FSRAM for the tag RAM, and an upper order address latch. Eight write enables are provided for byte write control. PD0PD4 identify density and functionality. This cache module is plug and pin compatible with the other members of Motorola's Triton chip set module family, the MCM72JG32SG66 (a 256K byte pipelined BurstRAM module) and the MCM72JG64SG66 (a 512K byte pipelined BurstRAM module).