The MCM63P636 is a 2Mbit synchronous fast static RAM designed to provide burstable, high performance, secondary cache for advanced microprocessors. It is organized as 64K words of 36 bits each. This device integrates input registers, an output register, a 2bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows for precise cycle control with the use of an external clock (K) and external strobe clock (SK). Addresses (SA), data inputs (DQx), and all control signals are clock (K) controlled through positiveedgetriggered noninverting registers. Data strobes STRBA, STRBA, STRBB, and STRBB are strobe clock (SK) controlled through positiveedgetriggered noninverting registers. Strobe clock, 180 degrees out of phase with clock (K), is only used with the data strobes such that they are centered with data output on read cycles. Burst sequences are initiated with ADS input pin, and subsequent burst addresses are generated internally by MCM63P636. Write cycles are internally selftimed and are initiated with address and control logic by the rising edge of the clock (K) input. This feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals. Special logic enables the memory to accept data on the rising edge of clock (K) a cycle after address and control signals. For read cycles, the SRAMs output data is temporarily stored by an edgetriggered output register and then released to the output buffers at the second rising edge of clock (K) for a read latency of three cycles. Data strobes rise and fall with SRAM output to help external devices receiving the data to latch the data.