The MC14076B 4Bit Register consists of four Dtype flipflops operating synchronously from a common clock. OR gated outputdisable inputs force the outputs into a highimpedance state for use in bus organized systems. OR gated datadisable inputs cause the Q outputs to be fed back to the D inputs of the flipflops. Thus they are inhibited from changing state while the clocking process remains undisturbed. An asynchronous master root is provided to clear all four flipflops simultaneously independent of the clock or disable inputs.