The MC14015B dual 4bit static shift register is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4state serialinput/paralleloutput registers. Each register has independent Clock and Reset inputs with a single serial Data input. The register states are type D masterslave flipflops. Data is shifted from one stage to the next during the positivegoing clock transition. Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serialtoparallel conversion where low power dissipation and/or noise immunity is desired. Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic EdgeClocked FlipFlop Design -- Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive going edge of the clock pulse.