The DSP96002 is designed to support intensive graphic image and numeric processing. It is a dual-port, low-power, general purpose floating-point processor. The DSP includes 1024 words of data RAM (equally divided into X data and Y data memory), 1024 words of fullspeed on-chip Program RAM, two data ROMs, a dual-channel Direct Memory Access (DMA) controller, special on-chip bootstrap hardware, and On-Chip Emulation (OnCETM) debug circuitry. The Central Processing Unit (CPU) consists of three 32-bit execution units operating in parallel. The DSP96002 has two identical memory expansion ports with control lines to facilitate interfacing SRAMs, DRAMs (operating in their fast access modes), and Video RAMs (VRAMs). Each port can be configured as a Host Interface (HI), which facilitates easy interface with other processors for multiprocessor applications. Linear arrays of DSP96002s can be implemented without glue logic. The MPU-style programming model and instruction set allow straightforward generation of efficient, compact code. The high speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive applications that require floating-point processing and access to large memory subsystems.