The V58C2128(804/404/164)S is a four bank DDR DRAM organized as 4 banks x 4Mbit x 8 (804), 4 banks x 2Mbit x 16 (404), or 4 banks x 8Mbit x 4 (164). The V58C2128(804/404/164)S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are ocurring on both edges of DQS.