The V54C365804VD(L) is a four bank Synchronous DRAM organized as 4 banks x 2Mbit x 8. The V54C365804VD(L) achieves high speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.