The V54C365324V is a 67,108, 864 bits synchronous high data rate DRAM organized as 4 x 524,288 words by 32 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation.