|
|
|
|
| Partname: | V54C316162V-5 |
| Description: | 3.3V, 4K refresh ultra-high performance 1M x 16 SDRAM 2 banks x 512Kbit x 16, 5ns |
| Manufacturer: | Mosel Vitelic |
| Package: | TSOP II |
| Pins: | 50 |
| Oper. temp.: | 0 to 70 |
| Datasheet: | PDF (322K).
Click here to download *) |
The V54C316162V is a 16,777,216 bits synchronous high data rate DRAM organized as 2 x 524,288 words by 16 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation. |
|
Click here to download V54C316162V-5 Datasheet*) |
 |
| *)Datasheets downloading from ChipDocs is only for our members (paid service). REGISTER NOW for your membership. |
|
|
|
