The input track and hold consists of a low (4pF) capacitance input and a fast settling operational amplifier. The A/D conversion is accomplished through a pipeline approach, reducing the number of required comparators and latches. The non-over-lapping clocks required for this architecture are all internally generated. Clock generation circuitry requires only one 50% duty cycle clock input. The use of error correction throughout the A/D converter improves DNL. All bias voltages and currents required by the A/D converter are internally generated. The digital outputs are three-stateable.