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Description:2.5V, 2GHz Any Diff. In-to-LVDS Programmable Clock Divider/Fanout Buffer with Internal Termination
Datasheet:PDF (576K).
Click here to download *)

The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The SY89872U is part of Micrel's high-speed Precision Edge timing and distribution family. For 3.3V applications, consider the SY89873L. For applications that require an LVPECL output, consider the SY89872U. The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN). Refer to the "Timing Diagram."

Click here to download SY89872UMG Datasheet
Click here to download SY89872UMG Datasheet
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