The SY89829U is a High Performance dual 1:10 or single 1:20 LVPECL Clock Driver. The part is designed for use in low voltage (2.5V/3.3V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either LVDS or LVPECL by the CLK_SEL pin. The LVDS inputs include a 100 internal termination across the input pair, thus eliminating any need for external termination. The 2:1 input mux makes this device an ideal choice for redundant clock applications that need to switch between two reference clocks. The output enable (OE) is synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.