The SY89825U is a High Performance Bus Clock Driver with 22 differential LVPECL output pairs. This part is designed for use in low voltage (2.5V, 3.3V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either LVDS or LVPECL by the CLK_SEL pin. The LVDS input includes a 100 internal termination, thus eliminating the need for external termination. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control. The SY89825U features low pin-to-pin skew (35ps max.) --performance previously unachievable in a standard product having such a high number of outputs. The SY89825U is available in a single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew.