The SY89424V is a low-power Phase Locked Loop (PLL) based frequency synthesizer. The device is capable of generating up to 1GHz clock frequencies with a low-cost 1025MHz external series-resonant quartz crystal. One can also use PECL differential clock signals to drive this device instead of the quartz crystal. Operation of this chip is controlled by three select pins (S1, S2 and S3). S1 selects the divide ratio of 24 or 50 for the PLL. S2 and S3 select the output frequency. There are two pull-down resistor pins (PDR1 and PDR2). Each pin has an on-chip resistor that will control the output driver currents. When PDR1 and PDR2 pins are open, both outputs are normal open emitter PECL drivers. When PDR1 and PDR 2 pins are shorted to the outputs, on-chip pull down currents of 25mA (40mA at 5V VCC) are provided. Both output drivers are capable of driving 20 ohm clock lines. An output enable (OE) pin is available and it can be HIGH or left open for normal operation. When OE is LOW, a built-in Disable Timing Synchronizer will force the FOUT output to LOW at the completion of the HIGH clock cycle. The FOUT output remains HIGH during that time.