The SY87702L is a complete Clock Recovery and Data retiming integrated circuit for data rates from 28Mbps up to 2.5Gbps NRZ. The device is ideally suited for SONET/SDH/ ATM, Fibre Channel, and Gigabit Ethernet applications, as well as other high-speed data transmission applications. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. Onchip clock generation is performed through the use of a frequency multiplier PLL and can be used as a Clock Multiplier Unit (CMU). The integrated CMU can provide this clock signal at the TCLK outputs. Additionally, the TCLK output can be selected to provide a copy of the RCLK frequency.