The SY58025U features two ultra-fast, low jitter 2:1 differential muxes with a guaranteed maximum data or clock throughput of 10.7Gbps or 7GHz, respectively. The SY58025U differential inputs include a unique, internal termination design that allows access to the termination network through a VT pin. The device easily interfaces to different logic standards, both AC- and DCcoupled, without external resistor-bias and termination networks. The result is a clean, stub-free, low jitter interface solution. The differential CML output is optimized for 50 environments with internal 50 source termination and a 400mV output swing.