The S Y56016R i s a f ully d ifferential, l ow v oltage 1.2V/1.8V/2.5V C ML L ine D river/Receiver w ith i nput equalization. The SY56016R can process clock signals as fast as 5.0GHz or data patterns up to 6.4Gbps. The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to CML differential signals, without any level-shifting or termination resistor networks in the signal path. The differential input can also accept AC-coupled CML, LVPECL, and LVDS signals. Input voltages as small as 200mV (400mVPP) are applied before the 9", 18" or 27" FR4 transmission line. For ACcoupled input interface applications, an internal voltage reference is provided to bias the VT pin. The outputs are CML, with extremely fast rise/fall times guaranteed to be less than 80ps.