The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latches. When both LEN1 and LEN 2 are at a logic LOW, the latches are transparent, thus presenting the data from the multiplexers at the output pins. If either LEN1 or LEN2 (or both) are at a logic HIGH, the outputs are latched. The multiplexer operation is controlled by the Select (SEL0, SEL1) signals which select one of the four bits of input data at each mux to be passed through. The MR (Master Reset) signal operates asynchronously to take all outputs to a logic LOW.