The SY10/100E111AE/LE are low skew 1-to-9 differential drivers designed for clock distribution in mind. The SY10/ 100E111AE/LE's function and performance are similar to the popular SY10/100E111, with the improvement of lower jitter and the added feature of low voltage operation. It accepts one signal input, which can be either differential or single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided such that a logic HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. The E111AE/LE is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device.