The SY10/100H841L are single supply, low skew translating 1:4 clock drivers. The devices feature a 24mA TTL output stage, with AC performance specified into a 20pF load capacitance. A latch is provided on-chip. When LEN is LOW (or left open, in which case it is pulled low by the internal pulldowns) the latch is transparent. A HIGH on the enable pin (EN) forces all outputs LOW. As frequencies increase to 40MHz and above, precise timing and shaping of clock signals becomes extremely important. The H841 solves several clock distribution problems such as minimizing skew (300ps), maximizing clock fanout (24mA drive), and precise duty cycle control through a proprietary differential internal design. The 10K version is compatible with 10KH ECL logic levels. The 100K version is compatible with 100K levels.