The devices feature a 24mA TTL output stage with AC performance specified into a 50pF load capacitance. A latch is provided on-chip. When LEN is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the latch is transparent. A HIGH on the enable pin (EN) forces all outputs LOW. The 10H version is compatible with MECL 10KH ECL logic levels. The 100H version is compatible with 100K levels.