The SY10/100EP451L is a 6-bit fully differential register with common clock and single-ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All i nputs h ave a n i nternal 7 5k p ull-down r esistor. Differential i nputs h ave a n o verride c lamp. U nused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE +1.2V, the clamp will override and force the output to a default state.