The SY100E222L is a low-skew, low-jitter device capable of receiving a high-speed LVECL/LVPECL input in either a single-ended or differential configuration. For single-ended configurations, a VBB output reference is supplied by the SY100E222L. A 2:1 input multiplexer selects from two differential input pairs by means of the CLK_SEL input select. The internal programmable divider for each of the four banks generates a 1 or 2 frequency of the selected input. The 1/ 2 divider outputs can be asynchronously synchronized with the master reset (MR) input so that the outputs will start out in a known state. The 15 total outputs are partitioned into four independently selected output banks in a 2/3/4/6 fanout configuration. Each of the four banks can independently select the 1 or 2 output frequency by means of the four separate frequency select pins (FSELA-FSELD) inputs. The SY100E222L is pin-for-pin compatible with the MC100LVE222FA device.