The SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distribution in new, highperformance ECL systems. They accept one differential or single-ended input, with V BB u sed for single-ended operation. The signal is fanned out to nine identical differential outputs. An enable input is also provided such that a logic HIGH disables the device by forcing all Q outputs LOW and all /Q outputs HIGH. The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. Since the E111 shares a common set of "basic" processing with the other members of the ECLinPSTM family, wafer characterization at the point of device personalization allows for tighter control of parameters, including propagation delay.