The interleaved mode allow uP to access SRAM ( packet/host buffer ) through MX98726's local DMA channel. This way, no extra SRAM interface logic is needed on the host side. If high performance is desired, then shared memory mode is another alternative which allow host to access SRAM on its own by denying SRAM bus grant to MX98726 using simple hand shake protocol. Without SRAM bus grant, MX98726 will float its interface connected to the SRAM, therefore host can utilize its own memory subsystem to conduct its own SRAM access.