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Partname: | LMU112 |
Description: | 12 x 12-bit Parallel Multiplier |
Manufacturer: | |
Datasheet: | PDF (46.5K). Click here to download *) |
The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds's MPY112K. The A and B input operands are loaded into their respective registers on the rising edge of the separate clock inputs (CLK A and CLK B). Two's complement or unsigned |
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Click here to download LMU112 Datasheet*) |
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