The LTC4304 hot swappable 2-wire bus buffer allows I/O card insertion into a live backplane without corruption of the data and clock busses. When a connection is made, the LTC4304 provides bidirectional buffering, keeping the backplane and card capacitances isolated. If SDAOUT or SCLOUT is low for 30ms (typ), the LTC4304 automatically breaks the data and clock bus connection and FAULT will pull low. At this time the LTC4304 automatically generates up to 16 clock pulses on SCLOUT in an attempt to free the bus. A connection will be enabled automatically when the bus becomes free. A logic low on the ACC input enables the LTC4304's rise-time accelerators. A logic high on ACC disables the rise-time accelerators, which allows SDA and SCL bus pull-up voltages below VCC. During insertion, the SDA and SCL lines are precharged to 1V to minimize bus disturbances. When driven high, ENABLE allows the LTC4304 to connect after a stop bit or bus idle occurs. Driving ENABLE low breaks the connection between SDAIN and SDAOUT, SCLIN and SCLOUT. READY is an open drain output that indicates when the backplane and card sides are connected together.