The bridge is intended to adapt an ATA100 Disk drive to a Serial ATA Host. This chip is a drop-in solution that is compatible with existing ATA software drivers and will run on standard operating systems without modification. After the wakeup routine is completed between the Host and Bridge with both in alignment, the Bridge will wait for a Host to Device FIS then transfer the Task file parameters to the drive. Any Host to Device FIS will update the Drive Task File. Any Drive Interrupt will initiate a Device to Host FIS to update the Hosts shadow Registers. With any Drive Task File update, the Bridge will determine the future data transfer direction and transfer type. The DMA control decode in the Host to Device FIS will initiate an Ultra DMA transfer sequence to the transmit FIFO or from the receive FIFO. If a write transfer was decoded a DMA Activate FIS is transmitted to the Host then the Bridge will wait for a Data Host to Device FIS before initiating the Drive data transfer. For a read decode, the bridge will transmit a Data Device to Host FIS when the Drive data transfer starts. When a power management request primitive is received from the Host, the Bridge will respond with a power management acknowledge primitive then it will idle the Transmit Driver and enter a low power state. To exit this low power state, a wakeup routine must be initiated by the Host.