The LDIC's Serial ATA IP Core, LD-LLC-0001-050 provides link and transport layers. This macro is fully compliant to Serial ATA Gen.1. The bridge is intended to adapt an ATA 66, ATA 100, ATA 133, and ATA 150 Disk drive to a Serial ATA Host or Parallel host to serial ATA interface. The Parallel ATA block connects directly to an IDE HOST or an IDE DEVICE (or target). The PHY interface is based on an industry standard XGMII interface definition with some additional signals for usage in the Serial ATA environment. The PHY is connected to the ATA block of the IP by using the 20 bit transmit and separate 20 bit receive data bus. These two buses are sampled on the transmit clock (TBC) and the receive clock (RBC). Both PHY and the ATA/Serial ATA blocks can be tested individually or together. This is accomplished with the TEST_MUX and TEST_ENABLEN pins on the device.