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Partname: | ispLSI5256VE-100LT128 |
Description: | In-system programmable 3.3V SuperWIDE high density PLD. fmax 100 MHz, tpd 10 ns. |
Manufacturer: | Lattice Semiconductor Corp. |
Package: | TQFP |
Pins: | 128 |
Oper. temp.: | 0 to 70 |
Datasheet: | PDF (247K). Click here to download *) |
The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. |
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![Click here to download ispLSI5256VE-100LT128 Datasheet](../../../pndecoder/datasheets/LATIC/img/000098.gif) Click here to download ispLSI5256VE-100LT128 Datasheet*) |
![](http://www.chipdocs.com/common/img/1x10t.gif) |
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