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Partname: | IS61DDB42M36-300M3 |
Description: | 72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs |
Manufacturer: | |
Datasheet: | PDF (669K). Click here to download *) |
The 72Mb IS61DDB42M36 and IS61DDB44M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table on p.8 for a description of the basic operations of these DDR-II (Burst of 4) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: |
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