The ISSI IS42S32800B is a high-speed CMOS configured as a quad 2M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the 2M x 32 bit banks is organized as 4096 rows by 512 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence. Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command