The IS24L128 and IS24L256 are electrically erasable PROM devices that use the standard 2-wire interface for communications. The IS24L128 and IS24CL256 contain a memory array of 128K-bits (16K x 8) and 256K-bits (32 x 8), respectively. Each device is organized into 64 byte pages for page write mode. This EEPROM operates in a voltage range of 1.8V to 3.6V for low voltage and standard voltage application levels. ISSI designed this device family to be a practical, low-power 2-wire EEPROM solution. The devices are available in 8-pin PDIP, 8-pin (JEDEC) SOIC, and 8-pin (EIAJ) SOIC packages. The IS24L128/256 maintains compatibility with the popular 2-wire bus protocol, so it is easy to design into applications implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as the IS24L128/256. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24L128/256 has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus.