The DDS accepts 48-bit center and offset frequency control information via a parallel processor interface. A 40-bit frequency tuning word can also be loaded via an asynchronous serial interface. Modulation control is provided by 3 external pins. The PH0 and PH1 pins select phase offsets of 0, 90, 180 and 270 degrees, while the ENOFR pin enables or zeros the offset frequency word to the phase accumulator. The parallel processor interface has an 8-bit write-only data input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe (WR), and a Write Enable (WE). The processor can update all registers simultaneously by loading a set of master registers, then transfer all master registers to the slave registers by asserting the UPDATE pin.