The Intersil HIP7010, J1850 Byte Level Interface Circuit, is a member of the Intersil family of low-cost multiplexed wiring ICs. The integrated functions of the HIP7010 provide the system designer with components key to building a "Class B" multiplexed communications network interface, which fully conforms to the VPW Multiplexed Wiring protocol specified in the SAE J1850 Standard. The HIP7010 is designed to interface with a wide variety of Host microcontrollers via a standard three wire, high-speed (1MHz), synchronous, serial interface. The HIP7010 automatically produces properly framed VPW messages, prepending the Start of Frame (SOF) symbol and calculating and appending the CRC check byte. All circuitry needed to decode incoming messages, to validate CRC bytes, and to detect Breaks, End of Data (EOD), Idle bus, and illegal symbols is included. InFrame Responses (IFRs) are fully supported for Type 1, Type 2, and Type 3 messages, with the appropriate Normalization Bit automatically generated. The HCMOS design allows proper opeSration at various input frequencies from 2MHz to 12MHz. Connection to the J1850 Bus is via a Intersil HIP7020.