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Partname:IN74AC533N
Description:Octal 3-state inverting transparent latch high-speed silicon-gate CMOS
Manufacturer:
Package:Plastic DIP
Pins:20
Oper. temp.:-40 to 85
Datasheet:PDF (206K).
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These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. The data appears as the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the highimpedance state. Thus, data may be latched even when the outputs are not enabled.

Click here to download IN74AC533N Datasheet
Click here to download IN74AC533N Datasheet
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