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| Partname: | IN74AC373DW |
| Description: | Octal 3-state noninverting transparent latch high-speed silicon-gate CMOS |
| Manufacturer: | |
| Package: | SOIC |
| Pins: | 20 |
| Oper. temp.: | -40 to 85 |
| Datasheet: | PDF (214K).
Click here to download *) |
These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the highimpedance state. Thus, data may be latched even when the outputs are not enabled. |
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Click here to download IN74AC373DW Datasheet*) |
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