The HYB 39S64400/800/160BT are four bank Synchronous DRAM's organized as 4 banks x 4MBit x4, 4 banks x 2 MBit x8 and 4 banks x 1 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates by employing a chip architecture that prefects multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using the Infineon advanced 0.2 m 64 MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for Synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rates than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3 V 0.3 V power supply and are available in TSOPII packages.