The IDT DDRIITM Burst of two SIO SRAMs are high-speed synchronous memories with independent, double-data-rate (DDR), read and write data ports with two data items passed with each read or write. Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. All buses associated with the DDRII SIO are unidirectional and can be optimized for signal integrity at very high bus speeds. Memory bandwidth is higher than DDR SRAM with bi-directional data buses as separate read and write ports eliminate bus turn around cycle. Separate read and write ports also enable easy depth expansion. Each port can be selected independantly with a R/W input shared among all SRAMs and provide a new LD load control signal for each bank. The DDRII SIO has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. The DDRII SIO has a single SDR address bus with multiplexed read and write addresses. The read/write and load control inputs are received on the first half of the clock cycle. The byte and nibble write signals are received on both halves of the clock cycle simultaneously with the data they are controlling on the data input bus. The DDRII SIO has echo clocks, which provide the user with a clock that is precisely timed to the data output, and tuned with matching impedance and signal quality. The user can use the echo clock for downstream clocking of the data. Echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are