The IDT85304-01 is a low skew, high performance 1-to-5 differential-to3.3V LVPECL clock generator-divider. It has two selectable clock inputs. The CLK/ xCLK pair can accept most standard differential input levels. The PCLK/ xPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the IDT8530401 ideal for those applications that demand well-defined performance and repeatability.