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| Partname: | IDT74FCT32932100PA |
| Description: | 3.3V low skew PLL-based CMOS clock driver |
| Manufacturer: | Integrated Device Technology |
| Package: | TSSOP |
| Pins: | 48 |
| Oper. temp.: | -40 to 85 |
| Datasheet: | PDF (131K).
Click here to download *) |
The FCT3932 uses phase-lock loop technology to lock the frequency and phase of the feedback to the input reference clock. It provides a large number of low skew outputs that are configurable in 16 different modes using the CNTRL 1-4 inputs. A dedicated output, Q_FB, is provided to supply the PLL feedback and it should be connected to the FEEDBACK input. Q_FB is located adjacent to FEEDBACK to minimize the delay in the feedback path. In order to offset any delay in the output path from the FCT3932 output to a receiving device, |
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Click here to download IDT74FCT32932100PA Datasheet*) |
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