The IDT72255/72265 are monolithic, CMOS, high capacity, high speed, low power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, local area networks (LANs), and inter-processor communication. Both FIFOs have an 18-bit input port (Dn) and an 18-bit output port (Qn). The input port is controlled by a free-running clock (WCLK) and a data input enable pin (WEN). Data is written into the synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and enable pin (REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronously for dual clock operation. An output enable pin (OE) is provided on the read port for three-state control of the outputs.