There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated. The IDT71V65602/5802 have an on-chip burst counter. In the burst mode, the IDT71V65602/5802 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. TheLBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/ LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). The IDT71V65602/5802 SRAM utilize IDT's latest high-performance CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA).